Convert CONFIG_PCIE1 et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 56a1650..a639dba 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -81,16 +81,13 @@
 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (128 << 10)
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     (0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START   (0x11000000)
@@ -98,10 +95,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST     0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_START   0xf8f80000
-#else
-#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR
-#define CONFIG_SYS_MPC85XX_NO_RESETVEC
-#endif
 #endif /* not CONFIG_TPL_BUILD */
 #endif
 
@@ -109,25 +102,16 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
-
-#define CONFIG_LBA48
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_SYS_CCSRBAR             0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
@@ -182,7 +166,6 @@
  * 0xf8f8_0000 0xf8ff_ffff     L2 SRAM         Up to 512K cacheable
  *   (early boot only)
  * 0xff80_0000 0xff80_7fff     NAND flash      32K non-cacheable       CS1/0
- * 0xff98_0000 0xff98_ffff     PMC             64K non-cacheable       CS2
  * 0xffa0_0000 0xffaf_ffff     CPLD            1M non-cacheable        CS3
  * 0xffb0_0000 0xffbf_ffff     VSC7385 switch  1M non-cacheable        CS2
  * 0xffc0_0000 0xffc3_ffff     PCI IO range    256k non-cacheable
@@ -289,14 +272,6 @@
 #endif
 /* CPLD config size: 1Mb */
 
-#define CONFIG_SYS_PMC_BASE    0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS       CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
-                                       BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM   (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
-                                OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
-                                OR_GPCM_EAD)
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR                   "vscfw_addr=ef000000\0"
@@ -366,8 +341,6 @@
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #endif
 
-#define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
-
 /*
  * I2C2 EEPROM
  */
@@ -439,10 +412,7 @@
 /*
  * Environment
  */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#elif defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_ENV_RANGE       (3 * CONFIG_ENV_SIZE)
+#if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define SPL_ENV_ADDR           (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
@@ -456,17 +426,6 @@
 /*
  * USB
  */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-#endif
-
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        1
-#endif
 
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR