#else
#define CONFIG_SYS_CLK_FREQ 66666666
#endif
-#define CONFIG_DDR_CLK_FREQ 66666666
#define CONFIG_HWCONFIG
/*
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
/* I2C */
#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#endif
-#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
/*
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 1000000
-
#ifdef __SW_BOOT_NOR
#define __NOR_RST_CMD \
norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
__stringify(__NAND_RST_CMD)"\0" \
__stringify(__PCIE_RST_CMD)"\0"
-#define CONFIG_NFSBOOTCOMMAND \
+#define NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-#define CONFIG_HDBOOT \
+#define HDBOOT \
"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
"console=$consoledev,$baudrate $othbootargs;" \
"usb start;" \
"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
"bootm $norbootaddr - $norfdtaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs " \
"ramdisk_size=$ramdisk_size;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
+#define CONFIG_BOOTCOMMAND HDBOOT
#endif /* __CONFIG_H */