#if defined(CONFIG_TARGET_P1020MBG)
#define CONFIG_BOARDNAME "P1020MBG-PC"
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#if defined(CONFIG_TARGET_P1020UTM)
#define CONFIG_BOARDNAME "P1020UTM-PC"
-#define CONFIG_P1020
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
#define __SW_BOOT_SD 0x50
#if defined(CONFIG_TARGET_P1020RDB_PC)
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_BOARDNAME "P1020RDB-PD"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0x03
"57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
#endif
-#if defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1021
#define CONFIG_QE
#define CONFIG_VSC7385_ENET
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
#endif
#endif
-#if defined(CONFIG_P1024RDB)
+#if defined(CONFIG_TARGET_P1024RDB)
#define CONFIG_BOARDNAME "P1024RDB"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1024
#define CONFIG_SLIC
#define __SW_BOOT_MASK 0xf3
#define __SW_BOOT_NOR 0x00
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P1025RDB)
+#if defined(CONFIG_TARGET_P1025RDB)
#define CONFIG_BOARDNAME "P1025RDB"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1025
#define CONFIG_QE
#define CONFIG_SLIC
#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB-PCA"
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P2020
#define CONFIG_VSC7385_ENET
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define CONFIG_LIBATA
#define CONFIG_LBA48
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_SYS_CLK_FREQ 100000000
#else
#define CONFIG_SYS_CLK_FREQ 66666666
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_TARGET_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
#else
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#endif /* CONFIG_QE */
-#ifdef CONFIG_P1025RDB
+#ifdef CONFIG_TARGET_P1025RDB
/*
* QE UEC ethernet configuration
*/
#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
#endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_P1025RDB */
+#endif /* CONFIG_TARGET_P1025RDB */
/*
* Environment