Remove remnants of obsolete CONFIG_SYS_GBL_DATA_SIZE comments

[platform/kernel/u-boot.git] / include / configs / omap3_zoom1.h

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 1e88dc0..9183849 100644 (file)
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -32,7 +32,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA8     1       /* This is an ARM V7 CPU core */
+#define CONFIG_ARMV7           1       /* This is an ARM V7 CPU core */
 #define CONFIG_OMAP            1       /* in a TI OMAP core */
 #define CONFIG_OMAP34XX                1       /* which is a 34XX */
 #define CONFIG_OMAP3430                1       /* which is in a 3430 */
@@ -61,14 +61,14 @@
 #define CONFIG_INITRD_TAG              1
 #define CONFIG_REVISION_TAG            1
 
+#define CONFIG_OF_LIBFDT               1
+
 /*
  * Size of malloc() pool
  */
 #define CONFIG_ENV_SIZE                        (128 << 10)     /* 128 KiB */
                                                /* Sector */
 #define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (128 << 10))
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* bytes reserved for */
-                                               /* initial data */
 
 /*
  * Hardware drivers
@@ -237,6 +237,12 @@
 #define CONFIG_SYS_LOAD_ADDR           (OMAP34XX_SDRC_CS0)     /* default */
                                                        /* load address */
 
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE       0x800
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - \
+                                        GENERATED_GBL_DATA_SIZE)
 /*
  * OMAP3 has 12 GP timers, they can be driven by the system clock
  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
@@ -278,12 +284,11 @@
 #define PISMO1_NAND_SIZE               GPMC_SIZE_128M
 #define PISMO1_ONEN_SIZE               GPMC_SIZE_128M
 
-#define CONFIG_SYS_MAX_FLASH_SECT      520     /* max number of sectors on */
-                                               /* one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of flash banks */
 #define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 2 sectors */
 
-#define CONFIG_SYS_FLASH_BASE          boot_flash_base
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE          PISMO1_NAND_BASE
+#endif
 
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
@@ -293,31 +298,8 @@
 #define ONENAND_ENV_OFFSET             0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET              0x260000 /* environment starts here */
 
-#define CONFIG_SYS_ENV_SECT_SIZE       boot_flash_sec
-#define CONFIG_ENV_OFFSET              boot_flash_off
+#define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)     /* 128 KiB */
+#define CONFIG_ENV_OFFSET              SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
 
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS       (CONFIG_SYS_MAX_FLASH_BANKS + \
-                                       CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK    CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS     1
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
-
 #endif                         /* __CONFIG_H */