/*
* High Level Configuration Options
*/
-#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
+#define CONFIG_OF_LIBFDT 1
+
/*
* Size of malloc() pool
* Total Size Environment - 256k
*/
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
- /* initial data */
/*--------------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
-/* DDR - I use Infineon DDR */
-#define CONFIG_OMAP3_INFINEON_DDR 1
-
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
*/
#if defined(CONFIG_CMD_MMC)
+#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
-#define CONFIG_OMAP3_MMC 1
+#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
#endif
*/
#if defined(CONFIG_CMD_NET)
-#define CONFIG_NET_MULTI
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
-#endif
-
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C 1
-
/*--------------------------------------------------------------------------*/
/*
* - rest for filesystem
*/
-/*--------------------------------------------------------------------------*/
-
-#ifndef __ASSEMBLY__
-extern unsigned int boot_flash_base;
-extern volatile unsigned int boot_flash_env_addr;
-extern unsigned int boot_flash_off;
-extern unsigned int boot_flash_sec;
-extern unsigned int boot_flash_type;
-#endif
+#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */