/* High Level Configuration Options */
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
-
#include <configs/ti_omap3_common.h>
-#ifdef CONFIG_SPL_BUILD
-/* select serial console configuration for SPL */
-#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
-#endif
-
-
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
-#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* Board NAND Info. */
#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
"ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
"nfsrootpath=/opt/nfs-exports/omap\0" \
"autoload=no\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"loadfdt=mmc rescan; " \
"load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
"mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#define CONFIG_SYS_FLASH_BASE 0x10000000
#endif
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x4000000
+
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE