/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
+
/* Clock config to target*/
#define PRCM_CONFIG_II 1
/* #define PRCM_CONFIG_III 1 */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
-#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
/*
* SMC91c96 Etherent
*/
-#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-
/*
* Command line configuration.
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define SECTORSIZE 512
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-
-#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
-#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
-#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
-#define NAND_WAIT_READY(nand) udelay(10)
-
-#define NAND_NO_RB 1
-
-#define CONFIG_SYS_NAND_WP
-#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
-#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
-
-#define NAND_CTL_CLRALE(nandptr)
-#define NAND_CTL_SETALE(nandptr)
-#define NAND_CTL_CLRCLE(nandptr)
-#define NAND_CTL_SETCLE(nandptr)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
/*
* Miscellaneous configurable options
*/
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_APTIX
-#define V_PROMPT "OMAP2420 Aptix # "
+# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
#else
-#define V_PROMPT "OMAP242x H4 # "
+# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
#endif
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT V_PROMPT
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE SZ_128K /* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
#define PHYS_FLASH_SIZE_2 SZ_32M
+#define PHYS_SRAM 0x4020F800
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
*/
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
+
#endif /* __CONFIG_H */