Merge branch 'origin'

[platform/kernel/u-boot.git] / include / configs / o2dnt.h

diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
index 12a732d..5c05a74 100644 (file)
--- a/include/configs/o2dnt.h
+++ b/include/configs/o2dnt.h
@@ -56,7 +56,7 @@
  */
 #define CONFIG_PCI             1
 #define CONFIG_PCI_PNP         1
-#define CONFIG_PCI_SCAN_SHOW   1
+/* #define CONFIG_PCI_SCAN_SHOW        1 */
 
 #define CONFIG_PCI_MEM_BUS     0x40000000
 #define CONFIG_PCI_MEM_PHYS    CONFIG_PCI_MEM_BUS
@@ -69,7 +69,7 @@
 #define CFG_XLB_PIPELINING     1
 
 #define CONFIG_NET_MULTI       1
-#define CONFIG_EEPRO100                1
+#define CONFIG_EEPRO100
 #define CFG_RX_ETH_BUFFER      8  /* use 8 rx buffer on eepro100  */
 #define CONFIG_NS8382X         1
 
@@ -90,7 +90,6 @@
                                CFG_CMD_FAT     | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_NFS     | \
-                               CFG_CMD_SNTP    | \
                                CFG_CMD_MII     | \
                                CFG_CMD_PING    | \
                                ADD_PCI_CMD     )
@@ -118,16 +117,16 @@
 #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
        "netdev=eth0\0"                                                 \
        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=$(serverip):$(rootpath)\0"                     \
+               "nfsroot=${serverip}:${rootpath}\0"                     \
        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "addip=setenv bootargs $(bootargs) "                            \
-               "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
-               ":$(hostname):$(netdev):off panic=1\0"                  \
+       "addip=setenv bootargs ${bootargs} "                            \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+               ":${hostname}:${netdev}:off panic=1\0"                  \
        "flash_nfs=run nfsargs addip;"                                  \
-               "bootm $(kernel_addr)\0"                                \
+               "bootm ${kernel_addr}\0"                                \
        "flash_self=run ramargs addip;"                                 \
-               "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
-       "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
+               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
        "rootpath=/opt/eldk/ppc_82xx\0"                                 \
        "bootfile=/tftpboot/MPC5200/uImage\0"                           \
        ""
@@ -138,8 +137,20 @@
 /*
  * IPB Bus clocking configuration.
  */
-#undef CFG_IPBSPEED_133                /* define for 133MHz speed */
+#define CFG_IPBSPEED_133               /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66                        /* define for 66MHz speed */
+#endif
 #endif
+
 /*
  * I2C configuration
  */
@@ -158,6 +169,7 @@
  * 0x50 ... 0x57 each 256 bytes in size
  *
  */
+#define CFG_I2C_FRAM
 #define CFG_I2C_EEPROM_ADDR            0x50    /* 1010000x */
 #define CFG_I2C_EEPROM_ADDR_LEN                1
 #define CFG_EEPROM_PAGE_WRITE_BITS     3
@@ -225,8 +237,8 @@
 /*
  * GPIO configuration
  */
-//#define CFG_GPS_PORT_CONFIG  0x10002004
-#define CFG_GPS_PORT_CONFIG    0x00002004 //no CAN
+/*#define CFG_GPS_PORT_CONFIG  0x10002004 */
+#define CFG_GPS_PORT_CONFIG    0x00002006      /* no CAN */
 
 /*
  * Miscellaneous configurable options
@@ -263,7 +275,16 @@
 
 #define CFG_BOOTCS_START       CFG_FLASH_BASE
 #define CFG_BOOTCS_SIZE                CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG         0x00047801
+
+#ifdef CFG_PCISPEED_66
+/*
+ * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
+ */
+#define CFG_BOOTCS_CFG         0x00057801 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG         0x00047801 /* for pci_clk = 33 MHz */
+#endif
+
 #define CFG_CS0_START          CFG_FLASH_BASE
 #define CFG_CS0_SIZE           CFG_FLASH_SIZE