+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX7ULP EVK board.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX7ULP_EVK_CONFIG_H
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_MAXARGS 256
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x60000000
#define PHYS_SDRAM_SIZE SZ_1G