#define CONFIG_DBG_MONITOR
#define PHYS_SDRAM_SIZE SZ_1G
-/* Uncomment to enable secure boot support */
-/* #define CONFIG_SECURE_BOOT */
-#define CONFIG_CSF_SIZE 0x4000
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
-#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RGMII
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE3000
-#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
-
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_CMD_EXPORTENV
-#undef CONFIG_CMD_IMPORTENV
-
/* I2C configs */
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI1 A flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
+
+#define UPDATE_M4_ENV \
+ "m4image=m4_qspi.bin\0" \
+ "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+ "update_m4_from_sd=" \
+ "if sf probe 0:0; then " \
+ "if run loadm4image; then " \
+ "setexpr fw_sz ${filesize} + 0xffff; " \
+ "setexpr fw_sz ${fw_sz} / 0x10000; " \
+ "setexpr fw_sz ${fw_sz} * 0x10000; " \
+ "sf erase 0x0 ${fw_sz}; " \
+ "sf write ${loadaddr} 0x0 ${filesize}; " \
+ "fi; " \
+ "fi\0" \
+ "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
#define CONFIG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
"rdinit=/linuxrc " \
"initrd_high=0xffffffff\0" \
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+#define CONFIG_DFU_ENV_SETTINGS \
+ "dfu_alt_info=image raw 0 0x800000;"\
+ "u-boot raw 0 0x4000;"\
+ "bootimg part 0 1;"\
+ "rootfs part 0 2\0" \
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ UPDATE_M4_ENV \
CONFIG_MFG_ENV_SETTINGS \
+ CONFIG_DFU_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"fdt_addr=0x83000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
+ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"fi; " \
"else run netboot; fi"
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKSIZE SZ_128K
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
+/* environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#else
#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX7
-#define CONFIG_USB_STORAGE
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_IMX_THERMAL
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_CS 0
+#define CONFIG_SF_DEFAULT_SPEED 40000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM 1
+#define FSL_QSPI_FLASH_SIZE SZ_64M
+#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
+#endif
+
#endif /* __CONFIG_H */