global: Migrate CONFIG_MXC_UART_BASE to CFG

[platform/kernel/u-boot.git] / include / configs / mx6sxsabreauto.h

diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 58cc3f0..3d0f6e4 100644 (file)
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -10,12 +10,9 @@
 
 #include "mx6_common.h"
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN          (3 * SZ_1M)
+#define CFG_MXC_UART_BASE              UART1_BASE
 
-#define CONFIG_MXC_UART_BASE           UART1_BASE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
        "script=boot.scr\0" \
        "image=zImage\0" \
        "console=ttymxc0\0" \
@@ -76,68 +73,33 @@
                        "bootz; " \
                "fi;\0"
 
-#define CONFIG_BOOTCOMMAND \
-          "mmc dev ${mmcdev};" \
-          "mmc dev ${mmcdev}; if mmc rescan; then " \
-                  "if run loadbootscript; then " \
-                          "run bootscript; " \
-                  "else " \
-                          "if run loadimage; then " \
-                                  "run mmcboot; " \
-                          "else run netboot; " \
-                          "fi; " \
-                  "fi; " \
-          "else run netboot; fi"
-
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CFG_SYS_SDRAM_BASE             PHYS_SDRAM
+#define CFG_SYS_INIT_RAM_ADDR  IRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE  IRAM_SIZE
 
 /* MMC Configuration */
-#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC3_BASE_ADDR
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED             100000
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
 
 /* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CFG_SYS_NAND_BASE           0x40000000
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 
 /* Network */
 
-#define CONFIG_FEC_MXC
-
 #define IMX_FEC_BASE                   ENET2_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x0
-
-#define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_ETHPRIME                 "FEC"
+#define CFG_FEC_MXC_PHYADDR          0x0
 
 #ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #endif
 
-#define CONFIG_SYS_FSL_USDHC_NUM       2
+#define CFG_SYS_FSL_USDHC_NUM  2
 
 #endif                         /* __CONFIG_H */