+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX6Q SabreAuto board.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX6SABREAUTO_CONFIG_H
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONSOLE_DEV "ttymxc3"
-#define CONFIG_MMCROOT "/dev/mmcblk0p2"
/* USB Configs */
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#include "mx6sabre_common.h"
+/* Falcon Mode */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#endif
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* NAND flash command */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-
/* NAND stuff */
-#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
-#define CONFIG_APBH_DMA
-#define CONFIG_APBH_DMA_BURST
-#define CONFIG_APBH_DMA_BURST8
/* PMIC */
#define CONFIG_POWER