+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* Configuration settings for Freescale MX53 low cost board.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000
-#define CONFIG_MISC_INIT_R
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_REVISION_TAG
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* Eth Configs */
-#define CONFIG_MII
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Command definition */
#define CONFIG_EXTRA_ENV_SETTINGS \
PPD_CONFIG_NFS \
- "bootlimit=10\0" \
"image=/boot/fitImage\0" \
"fdt_high=0xffffffff\0" \
"dev=mmc\0" \
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
/* FLASH and environment organization */
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
#define CONFIG_ENV_SIZE (10 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_CMD_FUSE