/* High Level Configuration Options */
-#define CONFIG_SYS_FSL_CLK
-
#include <asm/arch/imx-regs.h>
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
-
/*
* Hardware drivers
*/
-#define CONFIG_FSL_IIM
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CFG_MXC_UART_BASE UART1_BASE
/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS 0
-#define CONFIG_FSL_PMIC_CS 0
-#define CONFIG_FSL_PMIC_CLK 2500000
-#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
+#define CFG_FSL_PMIC_BUS 0
+#define CFG_FSL_PMIC_CS 0
+#define CFG_FSL_PMIC_CLK 2500000
+#define CFG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CFG_FSL_PMIC_BITLEN 32
/*
* MMC Configs
* */
-#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
-
-/*
- * Eth Configs
- */
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
+#define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
/* Framebuffer and LCD */
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ETHPRIME "FEC0"
-
-#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"fdt_file=imx51-babbage.dtb\0" \
"bootz; " \
"fi;\0"
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_MEMTEST_START 0x90000000
-#define CONFIG_SYS_MEMTEST_END 0x90010000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-#define CONFIG_SYS_DDR_CLKSEL 0
-#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
-#define CONFIG_SYS_MAIN_PWR_ON
+#define CFG_SYS_DDR_CLKSEL 0
+#define CFG_SYS_CLKTL_CBCDR 0x59E35100
+#define CFG_SYS_MAIN_PWR_ON
/*-----------------------------------------------------------------------
* environment organization
*/
-/*
- * Environment starts at CONFIG_ENV_OFFSET=0xC0000 = 768k = 768 * 1024 = 786432
- *
- * Detect overlap between U-Boot image and environment area in build-time
- *
- * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
- * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
- *
- * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
- * write the direct value here
- */
-#define CONFIG_BOARD_SIZE_LIMIT 785408
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
#endif