power:pmic: Rename CONFIG_PMIC* defines to CONFIG_POWER
[platform/kernel/u-boot.git] / include / configs / mx31pdk.h
index 4da6020..3b86c9e 100644 (file)
@@ -35,8 +35,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136                 /* This is an arm1136 CPU core */
 #define CONFIG_MX31                    /* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ  26000000
-#define CONFIG_MX31_CLK32      32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -71,9 +69,9 @@
 #define CONFIG_DEFAULT_SPI_MODE        (SPI_MODE_0 | SPI_CS_HIGH)
 
 /* PMIC Controller */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_SPI
-#define CONFIG_PMIC_FSL
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS    1
 #define CONFIG_FSL_PMIC_CS     2
 #define CONFIG_FSL_PMIC_CLK    1000000
@@ -85,7 +83,6 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_BAUDRATE                        115200
-#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
 
 /***********************************************************
  * Command definition
@@ -99,6 +96,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_BOOTZ
 
 /*
  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
 
 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_START       0x80000000
-#define CONFIG_SYS_MEMTEST_END         0x10000
+#define CONFIG_SYS_MEMTEST_END         0x80010000
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR           0x81000000
 #define CONFIG_CMDLINE_EDITING
 
 /*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE       (128 * 1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
  * Physical Memory Map
  */
 #define CONFIG_NR_DRAM_BANKS   1
 
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP         0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
-                                PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
-                                PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
-                                PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+                                PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+                                PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+                                PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
                                 PLL_MFN(12))
 
 #define ESDMISC_MDDR_SETUP     0x00000004