#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_XILINX_405 1
#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR
#define CFG_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH
-#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */
/* following are used only if env is in EEPROM */
-#ifdef CFG_ENV_IS_IN_EEPROM
+#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CFG_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-
-/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/