#define CONFIG_CPM2 1 /* Has a CPM2 */
-#undef DEBUG
+/* Do boardspecific init */
+#define CONFIG_BOARD_EARLY_INIT_R 1
/*
* Select serial console configuration
/*
* Default environment settings
*/
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "u-boot_addr=100000\0" \
- "kernel_addr=200000\0" \
- "fdt_addr=400000\0" \
- "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
- "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
- "bootfile=/tftpboot/mgcoge/uImage\0" \
- "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
- "load=tftp ${u-boot_addr} ${u-boot}\0" \
- "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
- "cp.b ${u-boot_addr} fe000000 ${filesize};" \
- "prot on fe000000 fe03ffff\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addcon=setenv bootargs ${bootargs} console=ttyCPM0,,${baudrate}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:on panic=1 " \
- "console=${console}\0" \
- "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
- "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcon;"\
- "bootm ${kernel_addr} - ${fdt_addr}\0" \
- "net_self=tftp ${kernel_addr} ${bootfile}; " \
- "tftp ${fdt_addr} ${fdt_file}; " \
- "tftp ${ramdisk_addr} ${ramdisk_file}; " \
- "run ramargs addip; " \
- "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "u-boot_addr=100000\0" \
+ "kernel_addr=200000\0" \
+ "fdt_addr=400000\0" \
+ "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
+ "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
+ "bootfile=/tftpboot/mgcoge/uImage\0" \
+ "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
+ "load=tftp ${u-boot_addr} ${u-boot}\0" \
+ "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
+ "cp.b ${u-boot_addr} fe000000 ${filesize};" \
+ "prot on fe000000 fe03ffff\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
+ "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "net_self=tftp ${kernel_addr} ${bootfile}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${ramdisk_addr} ${ramdisk_file}; " \
+ "run ramargs addip; " \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_SIZE 32
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+
+#define CFG_FLASH_BASE_1 0x50000000
+#define CFG_FLASH_SIZE_1 64
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE_1 }
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
-#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_FLASH
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE 0x20000
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#endif /* CFG_ENV_IS_IN_FLASH */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
#define CFG_IMMR 0xF0000000
#define CFG_HRCW_MASTER 0x0604b211
/* No slaves */
-#define CFG_HRCW_SLAVE1 0
-#define CFG_HRCW_SLAVE2 0
-#define CFG_HRCW_SLAVE3 0
-#define CFG_HRCW_SLAVE4 0
-#define CFG_HRCW_SLAVE5 0
-#define CFG_HRCW_SLAVE6 0
-#define CFG_HRCW_SLAVE7 0
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
* ---- --- ------- ------ ------
* 0 60x GPCM 8 bit FLASH
* 1 60x SDRAM 32 bit SDRAM
+ * 3 60x GPCM 8 bit GPIO/PIGGY
+ * 5 60x GPCM 16 bit CFG-Flash
*
*/
/* Bank 0 - FLASH
PSDMR_WRC_1C |\
PSDMR_CL_2)
+/* GPIO/PIGGY on CS3 initialization values
+*/
+#define CFG_PIGGY_BASE 0x30000000
+#define CFG_PIGGY_SIZE 128
+
+#define CFG_BR3_PRELIM ((CFG_PIGGY_BASE & BRx_BA_MSK) |\
+ BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_PIGGY_SIZE) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_3_CLK | ORxG_TRLX )
+
+/* CFG-Flash on CS5 initialization values
+*/
+#define CFG_BR5_PRELIM ((CFG_FLASH_BASE_1 & BRx_BA_MSK) |\
+ BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
+
+#define CFG_OR5_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE_1) |\
+ ORxG_CSNT | ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK | ORxG_TRLX )
+
#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
/* pass open firmware flat tree */
projects / platform / kernel / u-boot.git / blobdiff