Convert CONFIG_PCI_GT64120 to Kconfig

[platform/kernel/u-boot.git] / include / configs / maxbcm.h

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index d378333..db84302 100644 (file)
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -6,6 +6,8 @@
 #ifndef _CONFIG_DB_MV7846MP_GP_H
 #define _CONFIG_DB_MV7846MP_GP_H
 
+#include <linux/sizes.h>
+
 /*
  * High Level Configuration Options (easy to change)
  */
@@ -15,27 +17,13 @@
  * for DDR ECC byte filling in the SPL before loading the main
  * U-Boot into it.
  */
-#define CONFIG_SYS_TCLK                250000000       /* 250MHz */
-
-/*
- * Commands configuration
- */
 
 /* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MVTWSI
 #define CONFIG_I2C_MVTWSI_BASE0                MVEBU_TWSI_BASE
-#define CONFIG_SYS_I2C_SLAVE           0x0
-#define CONFIG_SYS_I2C_SPEED           100000
 
 /* SPI NOR flash default params, used by sf commands */
-#define CONFIG_SF_DEFAULT_SPEED                1000000
-#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_3
 
 /* Environment in SPI NOR flash */
-#define CONFIG_ENV_OFFSET              (1 << 20) /* 1MiB in */
-#define CONFIG_ENV_SIZE                        (64 << 10) /* 64KiB */
-#define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64KiB sectors */
 
 #define PHY_ANEG_TIMEOUT       8000    /* PHY needs a longer aneg time */
 
@@ -58,26 +46,7 @@
  * L2 cache thus cannot be used.
  */
 
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE           0x40004030
-#define CONFIG_SPL_MAX_SIZE            ((128 << 10) - 0x4030)
-
-#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
-
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
-#define CONFIG_DDR_FIXED_SIZE          (1 << 20)       /* 1GiB */
-#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
+#define CONFIG_SYS_SDRAM_SIZE          SZ_1G
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */