Coding style cleanup, update CHANGELOG

[platform/kernel/u-boot.git] / include / configs / lwmon5.h

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index ab42b59..ef9ab22 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -216,9 +216,6 @@
 /* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
 
-#define CMD_USB                        CFG_CMD_USB
-#else
-#define CMD_USB                        0       /* no USB on 440GRx             */
 #endif /* CONFIG_440EPX */
 
 /* Partitions */
@@ -226,36 +223,51 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_ISO_PARTITION
 
-#define CONFIG_COMMANDS       (CONFIG_CMD_DFL  |       \
-                              CFG_CMD_ASKENV   |       \
-                              CFG_CMD_DATE     |       \
-                              CFG_CMD_DHCP     |       \
-                              CFG_CMD_DIAG     |       \
-                              CFG_CMD_EEPROM   |       \
-                              CFG_CMD_ELF      |       \
-                              CFG_CMD_FAT      |       \
-                              CFG_CMD_I2C      |       \
-                              CFG_CMD_IRQ      |       \
-                              CFG_CMD_MII      |       \
-                              CFG_CMD_NET      |       \
-                              CFG_CMD_NFS      |       \
-                              CFG_CMD_PCI      |       \
-                              CFG_CMD_PING     |       \
-                              CFG_CMD_REGINFO  |       \
-                              CFG_CMD_SDRAM    |       \
-                              CMD_USB)
 
-#define CONFIG_SUPPORT_VFAT
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
  *----------------------------------------------------------------------*/
+#define CONFIG_SUPPORT_VFAT
+
 #define CFG_LONGHELP                   /* undef to save memory         */
 #define CFG_PROMPT             "=> "   /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE             1024    /* Console I/O Buffer Size      */
 #else
 #define CFG_CBSIZE             256     /* Console I/O Buffer Size      */
@@ -288,7 +300,6 @@
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT               /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
@@ -328,12 +339,24 @@
 #define CFG_EBC_CFG            0xb8400000
 
 /*-----------------------------------------------------------------------
+ * Graphics (Fujitsu Lime)
+ *----------------------------------------------------------------------*/
+/* SDRAM Clock frequency adjustment register */
+#define CFG_LIME_SDRAM_CLOCK   0xC1FC0000
+/* Lime Clock frequency is to set 133MHz */
+#define CFG_LIME_CLOCK_133MHZ  0x10000
+
+/* SDRAM Parameter register */
+#define CFG_LIME_MMR           0xC1FCFFFC
+/* SDRAM parameter value */
+#define CFG_LIME_MMR_VALUE     0x414FB7F2
+
+/*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
 #define CFG_GPIO_PHY1_RST      12
 #define CFG_GPIO_FLASH_WP      14
 #define CFG_GPIO_PHY0_RST      22
-#define CFG_GPIO_HUB_RST       50
 #define CFG_GPIO_WATCHDOG      58
 #define CFG_GPIO_LIME_S                59
 #define CFG_GPIO_LIME_RST      60
@@ -397,7 +420,7 @@
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)    DMA_ACK(0)      */      \
 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)    DMA_EOT/TC(0)   */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49  Unselect via TraceSelect Bit */      \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit */      \
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53  Unselect via TraceSelect Bit */      \
@@ -419,7 +442,7 @@
  *----------------------------------------------------------------------*/
 #define CFG_DCACHE_SIZE                (32<<10)  /* For AMCC 440 CPUs                  */
 #define CFG_CACHELINE_SIZE     32            /* ...                                */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5             /* log base 2 of the above value  */
 #endif
 
@@ -431,7 +454,7 @@
 #define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
 #define BOOTFLAG_WARM  0x02            /* Software reboot                      */
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX  2           /* which serial port to use */
 #endif