* (C) Copyright 2007-2013
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
-#ifdef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
-#define CONFIG_HOSTNAME lcd4_lwmon5
-#else
+
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_HOSTNAME lwmon5
-#endif
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
-#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
#define CONFIG_SYS_USB_DEVICE 0xe0000000
#define CONFIG_SYS_USB_HOST 0xe0000400
-#endif
/*
* Initial RAM & stack pointer
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
*/
-#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#endif
+
/* unused GPT0 COMP reg */
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
#define CONFIG_SYS_OCM_SIZE (16 << 10)
* Serial Port
*/
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_MBYTES_SDRAM 256
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#ifndef CONFIG_LCD4_LWMON5
#define CONFIG_DDR_ECC /* enable ECC */
-#endif
-#ifndef CONFIG_LCD4_LWMON5
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
CONFIG_SYS_POST_CPU | \
#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-#endif
/*
* I2C
/*
* Pass open firmware flat tree
*/
-#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/* Update size in "reg" property of NOR FLASH device tree nodes */
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
-#ifndef CONFIG_LCD4_LWMON5
/*
* USB/EHCI
*/
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-#endif
/*
* BOOTP options
/*
* Command line configuration.
*/
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_BMP
#endif
-#ifndef CONFIG_LCD4_LWMON5
#ifdef CONFIG_440EPX
#define CONFIG_CMD_USB
#endif
-#endif
/*
* Miscellaneous configurable options
#define CONFIG_SUPPORT_VFAT
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
-#ifndef CONFIG_LCD4_LWMON5
#ifndef DEBUG
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
#endif
#define CONFIG_WD_PERIOD 40000 /* in usec */
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
-#endif
/*
* For booting Linux, the board info and command line data
#define CONFIG_SYS_GPIO_PHY1_RST 12
#define CONFIG_SYS_GPIO_FLASH_WP 14
#define CONFIG_SYS_GPIO_PHY0_RST 22
+#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
#define CONFIG_SYS_GPIO_DSPIC_READY 51
#define CONFIG_SYS_GPIO_CAN_ENABLE 53
#define CONFIG_SYS_GPIO_LSB_ENABLE 54
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
#define CONFIG_SYS_GPIO_WATCHDOG 63
+#define GPIO49_VAL 1
+
/*
* PPC440 GPIO Configuration
*/
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * SPL related defines
- */
-#ifdef CONFIG_LCD4_LWMON5
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NOR_SUPPORT
-#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
-#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
-#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
-#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
-#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-/* Place BSS for SPL near end of SDRAM */
-#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
-#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
-
-#define CONFIG_SPL_OS_BOOT
-/* Place patched DT blob (fdt) at this address */
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
-
-#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
-
-/* Settings for real U-Boot to be loaded from NOR flash */
-#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_UBOOT_START 0x01002100
-
-#define CONFIG_SYS_OS_BASE 0xf8000000
-#define CONFIG_SYS_FDT_BASE 0xf87c0000
#endif
#endif /* __CONFIG_H */