Merge branch 'master' of /home/stefan/git/u-boot/lwmon5

[platform/kernel/u-boot.git] / include / configs / lwmon5.h

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 604b7d1..8ec4742 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -34,8 +34,8 @@
 #define CONFIG_SYS_CLK_FREQ    33300000        /* external freq to pll */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f      */
+#define CONFIG_BOARD_POSTCLK_INIT 1    /* Call board_postclk_init      */
 #define CONFIG_MISC_INIT_R     1       /* Call misc_init_r             */
-#define CONFIG_ADD_RAM_INFO    1       /* Print additional info        */
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -72,7 +72,6 @@
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache    */
-#define CFG_INIT_RAM_OCM       1               /* OCM as init ram      */
 #define CFG_INIT_RAM_ADDR      CFG_OCM_BASE    /* OCM                  */
 #define CFG_OCM_DATA_ADDR      CFG_OCM_BASE
 
@@ -143,15 +142,16 @@
 #endif
 
 /* POST support */
-#define CONFIG_POST            (CFG_POST_MEMORY   | \
-                                CFG_POST_ECC_ON   | \
+#define CONFIG_POST            (CFG_POST_CACHE    | \
                                 CFG_POST_CPU      | \
-                                CFG_POST_UART     | \
-                                CFG_POST_I2C      | \
-                                CFG_POST_CACHE    | \
-                                CFG_POST_FPU      | \
+                                CFG_POST_ECC_ON   | \
                                 CFG_POST_ETHER    | \
-                                CFG_POST_SPR)
+                                CFG_POST_FPU      | \
+                                CFG_POST_I2C      | \
+                                CFG_POST_MEMORY   | \
+                                CFG_POST_RTC      | \
+                                CFG_POST_SPR      | \
+                                CFG_POST_UART)
 
 #define CFG_POST_CACHE_ADDR    0x10000000      /* free virtual address         */
 #define CONFIG_LOGBUFFER
@@ -162,22 +162,29 @@
  *----------------------------------------------------------------------*/
 #define CONFIG_HARD_I2C                1               /* I2C with hardware support    */
 #undef CONFIG_SOFT_I2C                         /* I2C bit-banged               */
-#define CFG_I2C_SPEED          400000          /* I2C speed and slave address  */
+#define CFG_I2C_SPEED          100000          /* I2C speed and slave address  */
 #define CFG_I2C_SLAVE          0x7F
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR    (0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR    0x53    /* EEPROM AT24C128              */
+#define CFG_I2C_EEPROM_ADDR_LEN 2      /* Bytes of address             */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6   /* The Atmel AT24C128 has       */
+                                       /* 64 byte page write mode using*/
+                                       /* last 6 bits of the address   */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
 #define CONFIG_RTC_PCF8563     1               /* enable Philips PCF8563 RTC   */
 #define CFG_I2C_RTC_ADDR       0x51            /* Philips PCF8563 RTC address  */
+#define CFG_I2C_KEYBD_ADDR     0x56            /* PIC LWE keyboard             */
+
+#define        CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
+#if 0
+#define        CONFIG_AUTOBOOT_KEYED           /* Enable "password" protection */
+#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR      "  "    /* "password"   */
+#endif
 
-#define CONFIG_PREBOOT "echo;"                                         \
-       "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
-       "echo"
+#define        CONFIG_PREBOOT          "setenv bootdelay 15"
 
 #undef CONFIG_BOOTARGS
 
@@ -193,12 +200,13 @@
                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
                ":${hostname}:${netdev}:off panic=1\0"                  \
        "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
-       "flash_nfs=run nfsargs addip addtty;"                           \
+       "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+       "flash_nfs=run nfsargs addip addtty addmisc;"                   \
                "bootm ${kernel_addr}\0"                                \
-       "flash_self=run ramargs addip addtty;"                          \
+       "flash_self=run ramargs addip addtty addmisc;"                  \
                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-       "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
-               "bootm\0"                                               \
+       "net_nfs=tftp 200000 ${bootfile};"                              \
+               "run nfsargs addip addtty addmisc;bootm\0"              \
        "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
        "bootfile=/tftpboot/lwmon5/uImage\0"                            \
        "kernel_addr=FC000000\0"                                        \
@@ -226,6 +234,7 @@
 #define CONFIG_PHY_ADDR                3       /* PHY address, See schematics  */
 
 #define CONFIG_PHY_RESET        1      /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY 300
 
 #define CONFIG_HAS_ETH0
 #define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
@@ -391,9 +400,11 @@
 #define CFG_GPIO_PHY1_RST      12
 #define CFG_GPIO_FLASH_WP      14
 #define CFG_GPIO_PHY0_RST      22
-#define CFG_GPIO_WATCHDOG      58
+#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_EEPROM_INT_WP 57
 #define CFG_GPIO_LIME_S                59
 #define CFG_GPIO_LIME_RST      60
+#define CFG_GPIO_WATCHDOG      63
 
 /*-----------------------------------------------------------------------
  * PPC440 GPIO Configuration
@@ -462,7 +473,7 @@
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit */      \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58  Unselect via TraceSelect Bit */      \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit */      \
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit */      \