#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
-#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
+#define CFG_POST_ECC_ON CFG_POST_ECC
+#else
+#define CFG_POST_ECC_ON 0
+#endif
/* POST support */
-#define CONFIG_POST (CFG_POST_ECC)
-#endif
+#define CONFIG_POST (CFG_POST_CACHE | \
+ CFG_POST_CPU | \
+ CFG_POST_ECC_ON | \
+ CFG_POST_ETHER | \
+ CFG_POST_FPU | \
+ CFG_POST_I2C | \
+ CFG_POST_MEMORY | \
+ CFG_POST_RTC | \
+ CFG_POST_SPR | \
+ CFG_POST_UART)
+
+#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
+#define CONFIG_LOGBUFFER
+#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
-#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
+ /* 64 byte page write mode using*/
+ /* last 6 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-#define CFG_EEPROM_PAGE_WRITE_BITS 3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
"hostname=lwmon5\0" \
"netdev=eth0\0" \
"unlock=yes\0" \
+ "logversion=2\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
+ "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+ "flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
+ "flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addtty addmisc;bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/lwmon5/uImage\0" \
"kernel_addr=FC000000\0" \
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
-#define CMD_USB CFG_CMD_USB
-#else
-#define CMD_USB 0 /* no USB on 440GRx */
#endif /* CONFIG_440EPX */
/* Partitions */
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_DIAG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_I2C | \
- CFG_CMD_IRQ | \
- CFG_CMD_MII | \
- CFG_CMD_NET | \
- CFG_CMD_NFS | \
- CFG_CMD_PCI | \
- CFG_CMD_PING | \
- CFG_CMD_REGINFO | \
- CFG_CMD_SDRAM | \
- CMD_USB)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_SUPPORT_VFAT
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
+#define CONFIG_SUPPORT_VFAT
+
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_GPIO_PHY1_RST 12
#define CFG_GPIO_FLASH_WP 14
#define CFG_GPIO_PHY0_RST 22
-#define CFG_GPIO_WATCHDOG 58
+#define CFG_GPIO_EEPROM_EXT_WP 55
+#define CFG_GPIO_EEPROM_INT_WP 57
#define CFG_GPIO_LIME_S 59
#define CFG_GPIO_LIME_RST 60
+#define CFG_GPIO_WATCHDOG 63
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
projects / platform / kernel / u-boot.git / blobdiff