#define CONFIG_MPC823 1 /* This is a MPC823E CPU */
#define CONFIG_LWMON 1 /* ...on a LWMON board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
/* Default Ethernet MAC address */
#define CONFIG_ETHADDR 00:11:B0:00:00:00
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#endif
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
+#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */
+#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
#define CONFIG_LCD 1 /* use LCD controller ... */
#define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
* 3 = 0x3C+0x3F = F3 + F6 : enable test mode
*/
-#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
+#define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
/* "gatewayip=10.8.211.250\0" \ */
#define CONFIG_EXTRA_ENV_SETTINGS \
"key_magic2=3A+3C\0" \
"key_cmd2=echo *** Entering Update Mode ***;" \
"if fatload ide 0:3 10000 update.scr;" \
- "then autoscr 10000;" \
+ "then source 10000;" \
"else echo *** UPDATE FAILED ***;" \
"fi\0" \
"key_magic3=3C+3F\0" \
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 68 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
/* List of I2C addresses to be verified by POST */
#ifdef CONFIG_USE_FRAM
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR, \
+ }
#else /* Use EEPROM - which show up on 8 consequtive addresses */
-#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
- CONFIG_SYS_I2C_SYSMON_ADDR, \
- CONFIG_SYS_I2C_RTC_ADDR, \
- CONFIG_SYS_I2C_POWER_A_ADDR, \
- CONFIG_SYS_I2C_POWER_B_ADDR, \
- CONFIG_SYS_I2C_KEYBD_ADDR, \
- CONFIG_SYS_I2C_PICIO_ADDR, \
- CONFIG_SYS_I2C_EEPROM_ADDR+0, \
- CONFIG_SYS_I2C_EEPROM_ADDR+1, \
- CONFIG_SYS_I2C_EEPROM_ADDR+2, \
- CONFIG_SYS_I2C_EEPROM_ADDR+3, \
- CONFIG_SYS_I2C_EEPROM_ADDR+4, \
- CONFIG_SYS_I2C_EEPROM_ADDR+5, \
- CONFIG_SYS_I2C_EEPROM_ADDR+6, \
- CONFIG_SYS_I2C_EEPROM_ADDR+7, \
- }
+#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+ CONFIG_SYS_I2C_SYSMON_ADDR, \
+ CONFIG_SYS_I2C_RTC_ADDR, \
+ CONFIG_SYS_I2C_POWER_A_ADDR, \
+ CONFIG_SYS_I2C_POWER_B_ADDR, \
+ CONFIG_SYS_I2C_KEYBD_ADDR, \
+ CONFIG_SYS_I2C_PICIO_ADDR, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+0, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+1, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+2, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+3, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+4, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+5, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+6, \
+ CONFIG_SYS_I2C_EEPROM_ADDR+7, \
+ }
#endif /* CONFIG_USE_FRAM */
/*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MAR 0x00000088
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#endif /* __CONFIG_H */