/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017 NXP
+ * Copyright 2017, 2019-2020 NXP
* Copyright 2015 Freescale Semiconductor
*/
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
-#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
-
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_ENV_OFFSET (896 * 1024)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x20000
#endif
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#ifndef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x2000
-#endif
#endif
/* Debug Server firmware */
#define I2C_MUX_CH_DEFAULT 0x8
/* SPI */
-#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
-#define CONFIG_SPI_FLASH
-
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SST
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
-#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
-#define FSL_QSPI_FLASH_NUM 4
#endif
/*
* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
*/
#define FSL_QIXIS_BRDCFG9_QSPI 0x1
-#endif
-
/*
* MMC
*/
*/
#define RTC
#define CONFIG_RTC_DS3231 1
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
#define CONFIG_ID_EEPROM
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"mcmemsize=0x40000000\0" \
- "mcinitcmd=esbc_validate 0x580700000;" \
- "esbc_validate 0x580740000;" \
+ "mcinitcmd=esbc_validate 0x580640000;" \
+ "esbc_validate 0x580680000;" \
"fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
+#else
+#ifdef CONFIG_TFABOOT
+#define SD_MC_INIT_CMD \
+ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
+ "mmc read 0x80e00000 0x7000 0x800;" \
+ "fsl_mc start mc 0x80a00000 0x80e00000\0"
+#define IFC_MC_INIT_CMD \
+ "fsl_mc start mc 0x580a00000" \
+ " 0x580e00000 \0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "loadaddr=0x80100000\0" \
+ "loadaddr_sd=0x90100000\0" \
+ "kernel_addr=0x581000000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_start=0x581000000\0" \
+ "kernel_start_sd=0x8000\0" \
+ "kernel_load=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_size_sd=0x14000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernelheader_addr=0x580600000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernelheader_size=0x40000\0" \
+ "BOARD=ls2088aqds\0" \
+ "mcmemsize=0x70000000 \0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ IFC_MC_INIT_CMD \
+ BOOTENV \
+ "boot_scripts=ls2088aqds_boot.scr\0" \
+ "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0" \
+ "nor_bootcmd=echo Trying load from nor..;" \
+ "cp.b $kernel_addr $load_addr " \
+ "$kernel_size ; env exists secureboot && " \
+ "cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ "bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from SD ..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd && " \
+ "bootm $load_addr#$BOARD\0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"mcmemsize=0x40000000\0" \
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
-#endif /* CONFIG_SECURE_BOOT */
-
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_NXP_ESBC */
+
+#ifdef CONFIG_TFABOOT
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
+ "&& esbc_validate $load_addr; " \
+ "env exists mcinitcmd && run mcinitcmd " \
+ "&& mmc read 0x80d00000 0x6800 0x800 " \
+ "&& fsl_mc lazyapply dpl 0x80d00000; " \
+ "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+#define IFC_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
+ "&& fsl_mc lazyapply dpl 0x580d00000;" \
+ "run distro_bootcmd;run nor_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#endif
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E