configs: Migrate CONFIG_SYS_MAX_FLASH_BANKS to Kconfig

[platform/kernel/u-boot.git] / include / configs / ls2080aqds.h

diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index dc5f347..07cf59f 100644 (file)
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -9,24 +9,14 @@
 
 #include "ls2080a_common.h"
 
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_I2C_IFDR_DIV                0x7e
 #endif
 
 #define CONFIG_SYS_I2C_FPGA_ADDR       0x66
-#define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
-#define COUNTER_FREQUENCY_REAL         (CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY_REAL         (get_board_sys_clk()/4)
 
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #define SPD_EEPROM_ADDRESS1    0x51
 #define SPD_EEPROM_ADDRESS2    0x52
@@ -95,7 +85,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
@@ -105,7 +94,6 @@ unsigned long get_board_ddr_clk(void);
                                         CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_NAND_MAX_ECCPOS     256
 #define CONFIG_SYS_NAND_MAX_OOBFREE    2
 
@@ -124,8 +112,6 @@ unsigned long get_board_ddr_clk(void);
                                | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 /* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
                                        FTIM0_NAND_TWP(0x18)   | \
@@ -144,8 +130,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
-
 #define CONFIG_FSL_QIXIS       /* use common QIXIS code */
 #define QIXIS_LBMAP_SWITCH             0x06
 #define QIXIS_LBMAP_MASK               0x0f
@@ -218,7 +202,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
 
 #define CONFIG_SPL_PAD_TO              0x20000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 * 1024)
 #endif
 #else
@@ -267,15 +250,7 @@ unsigned long get_board_ddr_clk(void);
 #define I2C_MUX_CH_DEFAULT      0x8
 
 /* SPI */
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
-#endif
 
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SPI_FLASH_SPANSION
-#endif
 /*
  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
@@ -296,9 +271,7 @@ unsigned long get_board_ddr_clk(void);
  */
 #define RTC
 #define CONFIG_RTC_DS3231               1
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
-#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 
 /* EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_NXID