+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1088A_RDB_H
#include "ls1088a_common.h"
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_QIXIS_I2C_ACCESS
+#endif
#define SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#endif
#define CONFIG_SYS_IFC_CCR 0x01000000
#ifndef SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
#endif
+
+#ifndef SPL_NO_IFC
#define CONFIG_NAND_FSL_IFC
+#endif
+
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
+#endif
+
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_BRDCFG4_OFFSET 0x54
#define QIXIS_LBMAP_SWITCH 2
#define QIXIS_QMAP_MASK 0xe0
#define QIXIS_QMAP_SHIFT 5
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x20
#define QIXIS_LBMAP_SD 0x00
+#define QIXIS_LBMAP_EMMC 0x00
#define QIXIS_LBMAP_SD_QSPI 0x00
#define QIXIS_LBMAP_QSPI 0x00
#define QIXIS_RCW_SRC_SD 0x40
+#define QIXIS_RCW_SRC_EMMC 0x41
#define QIXIS_RCW_SRC_QSPI 0x62
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define I2C_SVDD_MONITOR_ADDR 0x4F
+
+#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088ARDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+
+#define PWM_CHANNEL0 0x0
+
/*
* I2C bus multiplexer
*/
#define I2C_RETIMER_ADDR 0x18
#define I2C_MUX_CH_DEFAULT 0x8
#define I2C_MUX_CH5 0xD
+
+#ifndef SPL_NO_RTC
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
+#endif
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#ifndef SPL_NO_QSPI
/* QSPI device */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_QSPI
#define FSL_QSPI_FLASH_SIZE (1 << 26)
#define FSL_QSPI_FLASH_NUM 2
#endif
+#endif
#define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
#define CONFIG_FSL_MEMAC
+#ifndef SPL_NO_ENV
/* Initial environment variables */
#if defined(CONFIG_QSPI_BOOT)
#define MC_INIT_CMD \
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"env exists mcinitcmd && run mcinitcmd && " \
- "mmc read 0x80200000 0x6800 0x800;" \
- "fsl_mc apply dpl 0x80200000;" \
+ "mmc read 0x80001000 0x6800 0x800;" \
+ "fsl_mc lazyapply dpl 0x80001000;" \
"bootm $load_addr#ls1088ardb\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
#define CONFIG_BOOTCOMMAND \
- "sf read 0x80200000 0xd00000 0x100000;" \
+ "sf read 0x80001000 0xd00000 0x100000;" \
"env exists mcinitcmd && env exists secureboot " \
" && sf read 0x80780000 0x780000 0x100000 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run qspi_bootcmd;" \
"env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND \
"env exists mcinitcmd && mmcinfo; " \
- "mmc read 0x80200000 0x6800 0x800; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
"env exists mcinitcmd && env exists secureboot " \
- " && mmc read 0x80780000 0x3800 0x10 " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
- "&& fsl_mc apply dpl 0x80200000;" \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
"run distro_bootcmd;run sd_bootcmd;" \
"env exists secureboot && esbc_halt;"
#endif
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_PHYLIB_10G
-#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_AQUANTIA
#define AQ_PHY_ADDR1 0x00
#define AQR105_IRQ_MASK 0x00000004
#define QSGMII2_PORT3_PHY_ADDR 0x1e
#define QSGMII2_PORT4_PHY_ADDR 0x1f
-#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
#define CONFIG_PHY_GIGE
#endif
+#endif
/* MMC */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
-#undef CONFIG_CMDLINE_EDITING
-#include <config_distro_defaults.h>
+#ifndef SPL_NO_ENV
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(SCSI, scsi, 0) \
- func(DHCP, dhcp, na)
+ func(SCSI, scsi, 0)
#include <config_distro_bootcmd.h>
+#endif
#include <asm/fsl_secure_boot.h>
projects / platform / kernel / u-boot.git / blobdiff