#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_board_ddr_clk(void);
-#endif
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_MISC_INIT_R
#endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define SYS_NO_FLASH
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
-#if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_EARLY_INIT
-#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
-#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
#endif
-#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
#define CONFIG_FSL_QIXIS
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
#define QIXIS_LBMAP_SWITCH 6
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO