Merge branch '2018-12-12-master-imports'

[platform/kernel/u-boot.git] / include / configs / ls1088aqds.h

diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 5674a5d..829c539 100644 (file)
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2017 NXP
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __LS1088A_QDS_H
@@ -10,9 +9,6 @@
 #include "ls1088a_common.h"
 
 
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
@@ -27,7 +23,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_MMC_ENV_DEV         0
 #define CONFIG_ENV_SIZE                        0x2000
 #else
-#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x20000
@@ -41,6 +36,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CLK_FREQ            100000000
 #define CONFIG_DDR_CLK_FREQ            100000000
 #else
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
 #define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
 #endif
@@ -89,21 +86,19 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NOR_CSOR    CSOR_NOR_ADM_SHIFT(12)
 #define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
                                FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TAVDS(0x6) | \
                                FTIM0_NOR_TEAHC(0x5))
 #define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
-                               FTIM1_NOR_TRAD_NOR(0x1a) |\
+                               FTIM1_NOR_TRAD_NOR(0x1a) | \
                                FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
-                               FTIM2_NOR_TCH(0x4) | \
-                               FTIM2_NOR_TWPH(0x0E) | \
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x8) | \
+                               FTIM2_NOR_TCH(0x8) | \
+                               FTIM2_NOR_TWPH(0xe) | \
                                FTIM2_NOR_TWP(0x1c))
 #define CONFIG_SYS_NOR_FTIM3   0x04000000
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifndef SYS_NO_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
@@ -197,7 +192,7 @@ unsigned long get_board_ddr_clk(void);
                                        | CSPR_MSEL_GPCM \
                                        | CSPR_V)
 
-#define CONFIG_SYS_FPGA_AMASK          IFC_AMASK(64*1024)
+#define SYS_FPGA_AMASK         IFC_AMASK(64 * 1024)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SYS_FPGA_CSOR           CSOR_GPCM_ADM_SHIFT(0)
 #else
@@ -226,7 +221,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR2               CONFIG_SYS_FPGA_CSPR
 #define CONFIG_SYS_CSPR2_FINAL         SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK2              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_AMASK2              SYS_FPGA_AMASK
 #define CONFIG_SYS_CSOR2               CONFIG_SYS_FPGA_CSOR
 #define CONFIG_SYS_CS2_FTIM0           SYS_FPGA_CS_FTIM0
 #define CONFIG_SYS_CS2_FTIM1           SYS_FPGA_CS_FTIM1
@@ -262,13 +257,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 #define CONFIG_SYS_CSPR3_EXT           CONFIG_SYS_FPGA_CSPR_EXT
 #define CONFIG_SYS_CSPR3               CONFIG_SYS_FPGA_CSPR
-#define CONFIG_SYS_CSPR3_FINAL         CONFIG_SYS_FPGA_CSPR_FINAL
-#define CONFIG_SYS_AMASK3              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSPR3_FINAL         SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3              SYS_FPGA_AMASK
 #define CONFIG_SYS_CSOR3               CONFIG_SYS_FPGA_CSOR
-#define CONFIG_SYS_CS3_FTIM0           CONFIG_SYS_FPGA_CS_FTIM0
-#define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_CS_FTIM1
-#define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_CS_FTIM2
-#define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_CS_FTIM3
+#define CONFIG_SYS_CS3_FTIM0           SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1           SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2           SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3           SYS_FPGA_CS_FTIM3
 #endif
 
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
@@ -329,7 +324,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* QSPI device */
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_FSL_QSPI
 #define FSL_QSPI_FLASH_SIZE            (1 << 26)
 #define FSL_QSPI_FLASH_NUM             2
 
@@ -346,7 +340,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START       0x80000000
 #define CONFIG_SYS_MEMTEST_END         0x9fffffff
 
@@ -359,7 +352,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_FSL_MEMAC
 
 /*  MMC  */
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
        QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
@@ -468,14 +460,11 @@ unsigned long get_board_ddr_clk(void);
 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 
-#define CONFIG_MII             /* MII PHY management */
 #define CONFIG_ETHPRIME                "DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
 
 #endif
 
-#undef CONFIG_CMDLINE_EDITING
-#include <config_distro_defaults.h>
 #define BOOT_TARGET_DEVICES(func) \
        func(USB, usb, 0) \
        func(MMC, mmc, 0) \