+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1046ARDB_H__
#include "ls1046a_common.h"
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x82000000
-#else
-#define CONFIG_SYS_TEXT_BASE 0x40100000
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_MISC_INIT_R
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
#endif
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
-#endif
-
#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
#ifdef CONFIG_EMMC_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
#endif
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI \
+ board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+#define CONFIG_SYS_UBOOT_BASE 0x40100000
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
#endif
#ifndef SPL_NO_IFC
#define CONFIG_ENV_OVERWRITE
#endif
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
+#else
#if defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
#endif
+#endif
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
-#define CONFIG_PHY_AQUANTIA
-#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x0
+#define FDT_SEQ_MACADDR_FROM_ENV
+
#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
#endif
#endif
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
#ifndef SPL_NO_MISC
#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+#else
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
"env exists secureboot && esbc_halt;"
#endif
#endif
+#endif
#include <asm/fsl_secure_boot.h>