#include "ls1046a_common.h"
-#define CONFIG_SYS_CLK_FREQ 100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define SPD_EEPROM_ADDRESS 0x51
-#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_UBOOT_BASE 0x40100000
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
-#endif
-
-#ifndef SPL_NO_IFC
-/* IFC */
-#define CONFIG_FSL_IFC
-/*
- * NAND Flash Definitions
- */
-#define CONFIG_NAND_FSL_IFC
#endif
#define CONFIG_SYS_NAND_BASE 0x7e800000
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x7) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
/*
* CPLD
*/
#define I2C_RETIMER_ADDR 0x18
/* PMIC */
-#define CONFIG_POWER
-#ifdef CONFIG_POWER
-#define CONFIG_POWER_I2C
-#endif
/*
* Environment
#define FM1_10GEC1_PHY_ADDR 0x0
#define FDT_SEQ_MACADDR_FROM_ENV
-
-#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
#endif
#ifndef SPL_NO_MISC
-#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;;"
#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
"env exists secureboot && esbc_halt;"
-#else
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
- "env exists secureboot && esbc_halt;;"
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
- "env exists secureboot && esbc_halt;"
-#endif
#endif
#endif