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Convert CONFIG_PHYLIB et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls1046aqds.h
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
index f4ecbdb..2a46c98 100644 (file)
--- a/include/configs/ls1046aqds.h
+++ b/include/configs/ls1046aqds.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __LS1046AQDS_H__
@@ -24,16 +23,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
-#define CONFIG_NR_DRAM_BANKS           2
 
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS             0x51
 #define CONFIG_SYS_SPD_BUS_NUM         0
 
-#ifndef CONFIG_SPL
-#define CONFIG_FSL_DDR_INTERACTIVE     /* Interactive debugging */
-#endif
-
 #define CONFIG_DDR_ECC
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
@@ -45,14 +39,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPI_FLASH_STMICRO       /* cs0 */
 #define CONFIG_SPI_FLASH_SST           /* cs1 */
 #define CONFIG_SPI_FLASH_EON           /* cs2 */
-#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SF_DEFAULT_BUS          1
-#define CONFIG_SF_DEFAULT_CS           0
-#endif
 #endif
 
 /* QSPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+       defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #ifdef CONFIG_FSL_QSPI
 #define CONFIG_SPI_FLASH_SPANSION
 #define FSL_QSPI_FLASH_SIZE            (1 << 24)
@@ -61,10 +52,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHYLIB_10G
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
@@ -112,9 +99,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY       0x00000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 #endif
@@ -232,7 +216,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (768 << 10)
 #endif
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#if defined(CONFIG_TFABOOT) || \
+       defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_I2C_EARLY_INIT
 #endif
@@ -287,6 +272,40 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FPGA_FTIM3          0x0
 #endif
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT           CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3               CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3              CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3               CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0           CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1           CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
+#else
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
@@ -354,6 +373,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM2           CONFIG_SYS_FPGA_FTIM2
 #define CONFIG_SYS_CS3_FTIM3           CONFIG_SYS_FPGA_FTIM3
 #endif
+#endif
 
 /*
  * I2C bus multiplexer
@@ -388,9 +408,6 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_SYS_LONGHELP            /* undef to save memory */
-#define CONFIG_AUTO_COMPLETE
 
 #define CONFIG_SYS_MEMTEST_START       0x80000000
 #define CONFIG_SYS_MEMTEST_END         0x9fffffff
@@ -407,26 +424,26 @@ unsigned long get_board_ddr_clk(void);
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#else
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_ENV_SIZE                        0x2000
-#define CONFIG_ENV_OFFSET              (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET              (3 * 1024 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV         0
-#define CONFIG_ENV_SIZE                        0x2000
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET              0x300000        /* 3MB */
-#define CONFIG_ENV_SECT_SIZE           0x10000
-#else
-#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x300000)
-#define CONFIG_ENV_SECT_SIZE           0x20000
-#define CONFIG_ENV_SIZE                        0x20000
+#endif
 #endif
 
 #define CONFIG_CMDLINE_TAG
 
 #undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND           "sf probe && sf read $kernel_load "    \
+                                       "e0000 f00000 && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND            "cp.b $kernel_start $kernel_load "     \
+                                       "$kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND         "mmc info; mmc read $kernel_load"     \
+                                       "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
+#else
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND             "sf probe && sf read $kernel_load "    \
                                        "e0000 f00000 && bootm $kernel_load"
@@ -434,6 +451,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTCOMMAND             "cp.b $kernel_start $kernel_load "     \
                                        "$kernel_size && bootm $kernel_load"
 #endif
+#endif
 
 #include <asm/fsl_secure_boot.h>
 
Domain: System / Kernel;