global: Migrate CONFIG_MXC_UART_BASE to CFG

[platform/kernel/u-boot.git] / include / configs / ls1046afrwy.h

diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 8425d17..5e03a96 100644 (file)
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -8,26 +8,22 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
-
-#define CONFIG_SYS_UBOOT_BASE          0x40100000
+#define CFG_SYS_UBOOT_BASE             0x40100000
 
 /*
  * NAND Flash Definitions
  */
 
-#define CONFIG_SYS_NAND_BASE           0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+#define CFG_SYS_NAND_BASE              0x7e800000
+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
 
-#define CONFIG_SYS_NAND_CSPR_EXT       (0x0)
-#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT  (0x0)
+#define CFG_SYS_NAND_CSPR      (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
                                | CSPR_PORT_SIZE_8      \
                                | CSPR_MSEL_NAND        \
                                | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_AMASK     IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_CSOR      (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
                                | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
@@ -35,36 +31,32 @@
                                | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
                                | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x7) | \
+#define CFG_SYS_NAND_FTIM0             (FTIM0_NAND_TCCST(0x7) | \
                                        FTIM0_NAND_TWP(0x18)   | \
                                        FTIM0_NAND_TWCHT(0x7) | \
                                        FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x32) | \
+#define CFG_SYS_NAND_FTIM1             (FTIM1_NAND_TADLE(0x32) | \
                                        FTIM1_NAND_TWBE(0x39)  | \
                                        FTIM1_NAND_TRR(0xe)   | \
                                        FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0xf) | \
+#define CFG_SYS_NAND_FTIM2             (FTIM2_NAND_TRAD(0xf) | \
                                        FTIM2_NAND_TREH(0xa) | \
                                        FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3          0x0
+#define CFG_SYS_NAND_FTIM3             0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
 
 /* IFC Timing Params */
-#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0              CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0               CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT              CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0          CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0         CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0          CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0              CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1              CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2              CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3              CFG_SYS_NAND_FTIM3
 
 /* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM              0
 #define I2C_RETIMER_ADDR                       0x18
 
 /* I2C bus multiplexer */
@@ -73,22 +65,19 @@
 #define I2C_MUX_CH_RTC                         0x1 /* Channel 0*/
 
 /* RTC */
-#define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR                0x51  /* Channel 0 I2C bus 0*/
-#define CONFIG_SYS_RTC_BUS_NUM                 0
+#define CFG_SYS_I2C_RTC_ADDR           0x51  /* Channel 0 I2C bus 0*/
+#define CFG_SYS_RTC_BUS_NUM                    0
 
 /*
  * Environment
  */
-#define CONFIG_SYS_FSL_QSPI_BASE       0x40000000
+#define CFG_SYS_FSL_QSPI_BASE  0x40000000
 
-#ifndef CONFIG_SPL_BUILD
 #undef BOOT_TARGET_DEVICES
 #define BOOT_TARGET_DEVICES(func) \
        func(MMC, mmc, 0) \
        func(USB, usb, 0) \
        func(DHCP, dhcp, na)
-#endif
 
 /* FMan */
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -100,8 +89,6 @@
 
 #define FDT_SEQ_MACADDR_FROM_ENV
 
-#define CONFIG_ETHPRIME                        "FM1@DTSEC3"
-
 #endif
 
 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "  \