global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / include / configs / ls1046afrwy.h

diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 791bb8d..48408f2 100644 (file)
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 #ifndef __LS1046AFRWY_H__
@@ -8,22 +8,11 @@
 
 #include "ls1046a_common.h"
 
-#define CONFIG_SYS_CLK_FREQ            100000000
-#define CONFIG_DDR_CLK_FREQ            100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
-
 #define CONFIG_SYS_UBOOT_BASE          0x40100000
 
-/* IFC */
-#define CONFIG_FSL_IFC
 /*
  * NAND Flash Definitions
  */
-#define CONFIG_NAND_FSL_IFC
 
 #define CONFIG_SYS_NAND_BASE           0x7e800000
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
@@ -42,8 +31,6 @@
                                | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
                                | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x7) | \
                                        FTIM0_NAND_TWP(0x18)   | \
                                        FTIM0_NAND_TWCHT(0x7) | \
@@ -58,11 +45,8 @@
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
-
 /* IFC Timing Params */
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NAND_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NAND_CSPR
@@ -74,13 +58,6 @@
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
 
 /* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM              0
-#define CONFIG_SYS_I2C_EEPROM_ADDR             0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
 #define I2C_RETIMER_ADDR                       0x18
 
 /* I2C bus multiplexer */
@@ -96,17 +73,16 @@
 /*
  * Environment
  */
-#define CONFIG_ENV_OVERWRITE
+#define CFG_SYS_FSL_QSPI_BASE  0x40000000
 
-#define CONFIG_SYS_MMC_ENV_DEV         0
-
-#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET              0x500000        /* 5MB */
-#define CONFIG_ENV_SECT_SIZE           0x40000         /* 256KB */
+#undef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+       func(MMC, mmc, 0) \
+       func(USB, usb, 0) \
+       func(DHCP, dhcp, na)
 
 /* FMan */
 #ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
 
 #define QSGMII_PORT1_PHY_ADDR          0x1c
 #define QSGMII_PORT2_PHY_ADDR          0x1d
@@ -115,17 +91,8 @@
 
 #define FDT_SEQ_MACADDR_FROM_ENV
 
-#define CONFIG_ETHPRIME                        "FM1@DTSEC3"
-
-#endif
-
-/* QSPI device */
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE            SZ_64M
-#define FSL_QSPI_FLASH_NUM             1
 #endif
 
-#undef CONFIG_BOOTCOMMAND
 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "  \
                           "env exists secureboot && esbc_halt;;"
 #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "   \