/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2016 Freescale Semiconductor
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#ifndef __LS1046A_COMMON_H
#define SPL_NO_IFC
#endif
-#define CONFIG_REMAKE_ELF
-#define CONFIG_GICV2
-
#include <asm/arch/config.h>
#include <asm/arch/stream_id_lsch2.h>
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
#endif
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
-#define CPU_RELEASE_ADDR secondary_boot_func
+#define CPU_RELEASE_ADDR secondary_boot_addr
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
#define CONFIG_SPL_STACK 0x1001f000
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN 0xa0000
#endif
+/* GPIO */
+
/* I2C */
-#define CONFIG_SYS_I2C
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
/* SATA */
#ifndef SPL_NO_SATA
-#define CONFIG_SCSI_AHCI_PLAT
-
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
-#define CONFIG_SYS_SCSI_MAX_LUN 1
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Command line configuration */
-
-/* MMC */
-#ifndef SPL_NO_MMC
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
#endif
/* FMan ucode */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FMAN_FW_ADDR 0x900000
-#else
-#ifdef CONFIG_SD_BOOT
-/*
- * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
- */
-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#elif defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
-#elif defined(CONFIG_NAND_BOOT)
-#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
-#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
-#endif
-#endif
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define LS1046A_BOOT_SRC_AND_HDR\
"boot_scripts=ls1046afrwy_boot.scr\0" \
"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
+#elif defined(CONFIG_TARGET_LS1046AQDS)
+#define LS1046A_BOOT_SRC_AND_HDR\
+ "boot_scripts=ls1046aqds_boot.scr\0" \
+ "boot_script_hdr=hdr_ls1046aqds_bs.out\0"
#else
#define LS1046A_BOOT_SRC_AND_HDR\
"boot_scripts=ls1046ardb_boot.scr\0" \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
+ "bootm_size=0x10000000\0" \
"fdt_addr=0x64f00000\0" \
- "kernel_addr=0x65000000\0" \
+ "kernel_addr=0x61000000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"&& sf read $kernelheader_addr_r $kernelheader_start " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
+ "nand_bootcmd=echo Trying load from nand..;" \
+ "nand info; nand read $load_addr " \
+ "$kernel_start $kernel_size; env exists secureboot " \
+ "&& nand read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
+ "nor_bootcmd=echo Trying load from nor..;" \
+ "cp.b $kernel_addr $load_addr " \
+ "$kernel_size; env exists secureboot " \
+ "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \