/* Link Definitions */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
#define CPU_RELEASE_ADDR secondary_boot_addr
/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
-
-/* SD boot SPL */
-#ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
-/*
- * HDR would be appended at end of image and copied to DDR along
- * with U-Boot image. Here u-boot max. size is 512K. So if binary
- * size increases then increase this size in case of secure boot as
- * it uses raw u-boot image instead of fit image.
- */
-#endif /* ifdef CONFIG_NXP_ESBC */
-#endif
+#define CFG_SYS_NS16550_CLK (get_serial_clock())
/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
/* I2C */
-/* SATA */
-#ifndef SPL_NO_SATA
-#define CONFIG_SYS_SATA AHCI_BASE_ADDR
-#endif
-
/* FMan ucode */
#ifndef SPL_NO_FMAN
-#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CFG_SYS_FM_MURAM_SIZE 0x60000
#endif
#endif
/* Miscellaneous configurable options */
-#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#define BOOT_TARGET_DEVICES(func) \
#endif
#ifndef SPL_NO_MISC
/* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \