configs: Migrate CMD_NAND*

[platform/kernel/u-boot.git] / include / configs / ls1046a_common.h

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 8ec1247..1b91676 100644 (file)
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -7,12 +7,30 @@
 #ifndef __LS1046A_COMMON_H
 #define __LS1046A_COMMON_H
 
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_QBMAN
+#define SPL_NO_FMAN
+#define SPL_NO_ENV
+#define SPL_NO_MISC
+#define SPL_NO_QSPI
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#endif
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
+#define SPL_NO_MMC
+#endif
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
+#define SPL_NO_IFC
+#endif
+
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_MP
 #define CONFIG_GICV2
 
 #include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
 
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
@@ -41,7 +59,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 
-#define CONFIG_BAUDRATE                        115200
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 /* SD boot SPL */
@@ -68,7 +85,19 @@
 #define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
                                        CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
-#define CONFIG_SYS_MONITOR_LEN         0xa0000
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE                         (16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN         0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
 #endif
 
 /* NAND SPL */
@@ -88,7 +117,7 @@
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_TEXT_BASE           0x10000000
-#define CONFIG_SPL_MAX_SIZE            0x1d000         /* 116 KiB */
+#define CONFIG_SPL_MAX_SIZE            0x17000         /* 90 KiB */
 #define CONFIG_SPL_STACK               0x1001f000
 #define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
@@ -109,43 +138,58 @@
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC_I2C4
 
+/* PCIe */
+#define CONFIG_PCIE1           /* PCIE controller 1 */
+#define CONFIG_PCIE2           /* PCIE controller 2 */
+#define CONFIG_PCIE3           /* PCIE controller 3 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
+
 /* Command line configuration */
-#define CONFIG_CMD_ENV
 
 /* MMC */
+#ifndef SPL_NO_MMC
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
+#endif
 
+#ifndef SPL_NO_QBMAN
 #define CONFIG_SYS_DPAA_QBMAN          /* Support Q/Bman */
+#endif
 
 /* FMan ucode */
+#ifndef SPL_NO_FMAN
 #define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
+#endif
 
 #ifdef CONFIG_SD_BOOT
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x820)
+#define CONFIG_SYS_FMAN_FW_ADDR                (512 * 0x4800)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
-#define CONFIG_SYS_FMAN_FW_ADDR                0x40300000
+#define CONFIG_SYS_FMAN_FW_ADDR                0x40900000
 #define CONFIG_ENV_SPI_BUS             0
 #define CONFIG_ENV_SPI_CS              0
 #define CONFIG_ENV_SPI_MAX_HZ          1000000
 #define CONFIG_ENV_SPI_MODE            0x03
 #elif defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR                (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR                (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR                0x60300000
+#define CONFIG_SYS_FMAN_FW_ADDR                0x60900000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@@ -157,6 +201,7 @@
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           128
 
+#ifndef SPL_NO_MISC
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
@@ -174,22 +219,24 @@
 #define CONFIG_BOOTARGS                        "console=ttyS0,115200 root=/dev/ram0 " \
                                        "earlycon=uart8250,mmio,0x21c0500 " \
                                        MTDPARTS_DEFAULT
+#endif
+
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE /* Boot args buffer */
 #define CONFIG_SYS_LONGHELP
+
+#ifndef SPL_NO_MISC
 #define CONFIG_CMDLINE_EDITING         1
+#endif
+
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS             64      /* max command args */
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
+#include <asm/arch/soc.h>
 
 #endif /* __LS1046A_COMMON_H */