#define CONFIG_LAYERSCAPE_NS_ACCESS
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
#endif
#define QSGMII_PORT4_PHY_ADDR 0x7
#define FM1_10GEC1_PHY_ADDR 0x1
-
-#define CONFIG_ETHPRIME "FM1@DTSEC3"
#endif
#endif