#define CONFIG_ARMV7_PSCI
-#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#endif
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW \
+ board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+#endif
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x40010000
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NO_FLASH
#endif
/*
* IFC Definitions
*/
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
* Serial Port
*/
#ifdef CONFIG_LPUART
-#define CONFIG_FSL_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
+#endif
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#endif
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* EEPROM */
-#ifndef CONFIG_SD_BOOT
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
/*
* MMC
#define CONFIG_DOS_PARTITION
/* SPI */
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
/* QSPI */
-#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE 0x40000000
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SPI_FLASH_STMICRO
+
+/* DSPI */
+#endif
/* DM SPI */
#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
#define CONFIG_CMD_SF
#define CONFIG_DM_SPI_FLASH
#endif
-#endif
/*
* Video
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#undef CONFIG_CMD_IMLS
+#endif
+
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LS102XA_NS_ACCESS
+#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define CONFIG_TIMER_CLK_FREQ 12500000
#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
- "initrd_high=0xcfffffff\0" \
- "fdt_high=0xcfffffff\0"
+ "initrd_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
- "initrd_high=0xcfffffff\0" \
- "fdt_high=0xcfffffff\0"
+ "initrd_high=0xffffffff\0" \
+ "fdt_high=0xffffffff\0"
#endif
/*
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
-#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
+#define CONFIG_SYS_QE_FW_ADDR 0x600c0000
/*
* Environment
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_CMD_BOOTZ
#define CONFIG_MISC_INIT_R
/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
+#endif
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CMD_BLOB
#include <asm/fsl_secure_boot.h>
-#endif
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#endif