/* SPDX-License-Identifier: GPL-2.0
- * Copyright 2016-2019 NXP Semiconductors
+ * Copyright 2016-2019 NXP
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/
#define CONFIG_DEEP_SLEEP
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
- "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
-#endif
-
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
- "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
-
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
#endif /* ifdef CONFIG_NXP_ESBC */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \