Merge tag 'next-20220328' of https://source.denx.de/u-boot/custodians/u-boot-video...

[platform/kernel/u-boot.git] / include / configs / ls1021atsn.h

diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index 996c970..3742203 100644 (file)
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -1,29 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0
- * Copyright 2016-2019 NXP Semiconductors
+ * Copyright 2016-2019 NXP
  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  */
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
-
-#define CONFIG_SYS_FSL_CLK
-
 #define CONFIG_DEEP_SLEEP
 
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
 /* XHCI Support - enabled by default */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 
-#define CONFIG_SYS_CLK_FREQ            100000000
-#define CONFIG_DDR_CLK_FREQ            100000000
-
 #define DDR_SDRAM_CFG                  0x470c0008
 #define DDR_CS0_BNDS                   0x008000bf
 #define DDR_CS0_CONFIG                 0x80014302
@@ -51,15 +41,7 @@
 #define SDRAM_CFG2_FRC_SR              0x80000000
 #define SDRAM_CFG_BI                   0x00000001
 
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI \
-               "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
-#endif
-
 #ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW \
-               "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
-
 #ifdef CONFIG_NXP_ESBC
 #define CONFIG_U_BOOT_HDR_SIZE         (16 << 10)
 #endif /* ifdef CONFIG_NXP_ESBC */
@@ -87,15 +69,12 @@
 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 #endif
 
-#define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        (1u * 1024 * 1024 * 1024)
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_CHIP_SELECTS_PER_CTRL   4
-
 /* Serial Port */
 #define CONFIG_SYS_NS16550_SERIAL
 #ifndef CONFIG_DM_SERIAL
@@ -104,23 +83,10 @@
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
 
 /* I2C */
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
-#else
-#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
-#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
-#endif
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1                /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2                /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3                /* enable I2C bus 3 */
 
 /* EEPROM */
-#define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x51
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 
 /* QSPI */
 #define FSL_QSPI_FLASH_SIZE            (1 << 24)
@@ -220,8 +186,6 @@
 #define CONFIG_SYS_MAXARGS             16      /* max number of command args */
 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_LOAD_ADDR           0x82000000
-
 #define CONFIG_LS102XA_STREAM_ID
 
 #define CONFIG_SYS_INIT_SP_OFFSET \