#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
-#endif
-
#ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_MAX_SIZE 0x1a000
-#define CONFIG_SPL_STACK 0x1001d000
-#define CONFIG_SPL_PAD_TO 0x1c000
-
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN 0xc0000
#endif
#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SPL_MAX_SIZE 0x1a000
-#define CONFIG_SPL_STACK 0x1001d000
-#define CONFIG_SPL_PAD_TO 0x1c000
-
#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* QIXIS Definitions
*/
-#define CONFIG_FSL_QIXIS
#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE 0x7fb00000
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CONFIG_LS102XA_STREAM_ID
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
/*
* Environment
*/