#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_ARMV7_PSCI_1_0
-
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_SYS_FSL_CLK
/*
* I2C
*/
-#ifndef CONFIG_DM_I2C
-#define CONFIG_SYS_I2C
+#if !CONFIG_IS_ENABLED(DM_I2C)
#else
#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#endif
+
/* EEPROM */
-#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* I2C bus multiplexer
* MMC
*/
-/* SPI */
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-/* QSPI */
-#define QSPI0_AMBA_BASE 0x40000000
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-
-/* DSPI */
-
-/* DM SPI */
-#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
-#define CONFIG_DM_SPI_FLASH
-#define CONFIG_SPI_FLASH_DATAFLASH
-#endif
-#endif
-
/*
* Video
*/
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_LS102XA_STREAM_ID
/*
* Environment
*/
-#define CONFIG_ENV_OVERWRITE
-
-#if defined(CONFIG_SD_BOOT)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#endif
#include <asm/fsl_secure_boot.h>
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */