Kconfig: USB: Migrate CONFIG_USB_EHCI to CONFIG_USB_EHCI_HCD

[platform/kernel/u-boot.git] / include / configs / ls1021aqds.h

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 53f0368..d13517c 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_LS102XA
-
 #define CONFIG_ARMV7_PSCI_1_0
 
 #define CONFIG_ARMV7_SECURE_BASE       OCRAM_BASE_S_ADDR
@@ -16,7 +14,6 @@
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_DEEP_SLEEP
 
@@ -28,11 +25,6 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
-/*
- * Generic Timer Definitions
- */
-#define GENERIC_TIMER_CLK              12500000
-
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
@@ -61,8 +53,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0xe8
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS             0x600
 
 #define CONFIG_SPL_TEXT_BASE           0x10000000
 #define CONFIG_SPL_MAX_SIZE            0x1a000
@@ -82,10 +72,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_TEXT_BASE           0x40010000
 #endif
 
-#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_SYS_NO_FLASH
-#endif
-
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
 #define CONFIG_SPL_FRAMEWORK
@@ -136,8 +122,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #endif
 
-#define CONFIG_FSL_CAAM                        /* Enable CAAM */
-
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
        !defined(CONFIG_QSPI_BOOT)
 #define CONFIG_U_QE
@@ -374,8 +358,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
 #endif
 
-#define CONFIG_BAUDRATE                        115200
-
 /*
  * I2C
  */
@@ -395,11 +377,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * MMC
  */
-#define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
-#define CONFIG_GENERIC_MMC
-
-#define CONFIG_DOS_PARTITION
 
 /* SPI */
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
@@ -424,7 +402,7 @@ unsigned long get_board_ddr_clk(void);
 /*#define CONFIG_HAS_FSL_DR_USB*/
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif
@@ -441,10 +419,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
-#define CONFIG_CMD_BMP
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 
@@ -503,23 +478,6 @@ unsigned long get_board_ddr_clk(void);
 /* PCIe */
 #define CONFIG_PCIE1           /* PCIE controller 1 */
 #define CONFIG_PCIE2           /* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF  0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE      0x00001000      /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF  0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE      0x00001000      /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS         0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF    0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE                0x00010000      /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS                0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF   0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE       0x08000000      /* 128M */
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW
@@ -532,7 +490,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200
-#define CONFIG_TIMER_CLK_FREQ          12500000
+#define COUNTER_FREQUENCY              12500000
 
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE           256
@@ -574,12 +532,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_LS102XA_STREAM_ID
 
-/*
- * Stack sizes
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE               (30 * 1024)
-
 #define CONFIG_SYS_INIT_SP_OFFSET \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \