Convert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / ls1021aqds.h

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 6c5aa40..748c04b 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -11,15 +11,8 @@
 
 #define CONFIG_SYS_FSL_CLK
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 #define CONFIG_DEEP_SLEEP
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
-
 #define CONFIG_SYS_INIT_RAM_ADDR       OCRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       OCRAM_SIZE
 
@@ -34,19 +27,7 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #endif
 
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
-#endif
-
 #ifdef CONFIG_SD_BOOT
-#ifdef CONFIG_SD_BOOT_QSPI
-#define CONFIG_SYS_FSL_PBL_RCW \
-       board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
-#else
-#define CONFIG_SYS_FSL_PBL_RCW \
-       board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
-#endif
-
 #define CONFIG_SPL_MAX_SIZE            0x1a000
 #define CONFIG_SPL_STACK               0x1001d000
 #define CONFIG_SPL_PAD_TO              0x1c000
@@ -60,15 +41,11 @@ unsigned long get_board_sys_clk(void);
 #endif
 
 #ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
-
 #define CONFIG_SPL_MAX_SIZE            0x1a000
 #define CONFIG_SPL_STACK               0x1001d000
 #define CONFIG_SPL_PAD_TO              0x1c000
 
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (400 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS    CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_PAGE_SIZE      2048
 #define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 
@@ -147,7 +124,6 @@ unsigned long get_board_sys_clk(void);
 /*
  * NAND Flash Definitions
  */
-#define CONFIG_NAND_FSL_IFC
 
 #define CONFIG_SYS_NAND_BASE           0x7e800000
 #define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
@@ -167,8 +143,6 @@ unsigned long get_board_sys_clk(void);
                                | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
                                | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 #define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x7) | \
                                        FTIM0_NAND_TWP(0x18)   | \
                                        FTIM0_NAND_TWCHT(0x7) | \
@@ -184,8 +158,6 @@ unsigned long get_board_sys_clk(void);
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 #endif
 
 /*
@@ -408,8 +380,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 
-#define CONFIG_CMDLINE_TAG
-
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR            0x01ee0200