Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u...

[platform/kernel/u-boot.git] / include / configs / ls1012aqds.h

diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 3829f1a..fb0d1ba 100644 (file)
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __LS1012AQDS_H__
@@ -12,7 +11,6 @@
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
-#define CONFIG_NR_DRAM_BANKS           2
 #define CONFIG_SYS_SDRAM_SIZE          0x40000000
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_SYS_MEMTEST_START       0x80000000
@@ -76,9 +74,7 @@
 
 /* DSPI */
 #define CONFIG_FSL_DSPI1
-#define CONFIG_DEFAULT_SPI_BUS 1
 
-#define CONFIG_CMD_SPI
 #define MMAP_DSPI          DSPI1_BASE_ADDR
 
 #define CONFIG_SYS_DSPI_CTAR0   1
@@ -101,11 +97,6 @@
                                DSPI_CTAR_DT(0))
 #define CONFIG_SPI_FLASH_EON /* cs3 */
 
-#define CONFIG_SF_DEFAULT_SPEED      10000000
-#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
-#define CONFIG_SF_DEFAULT_BUS        1
-#define CONFIG_SF_DEFAULT_CS         0
-
 /*  MMC  */
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
@@ -119,6 +110,5 @@
 #define CONFIG_SYS_MEMTEST_START       0x80000000
 #define CONFIG_SYS_MEMTEST_END         0x9fffffff
 
-#define CONFIG_MISC_INIT_R
-
+#include <asm/fsl_secure_boot.h>
 #endif /* __LS1012AQDS_H__ */