/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/*
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_SST /* cs1 */
#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_SPI_FLASH_EON /* cs3 */
#define CONFIG_PCIE1 /* PCIE controller 1 */