#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
-/* DDR board-specific timing parameters */
-#define CONFIG_MMDC_MDCTL 0x05180000
-#define CONFIG_MMDC_MDPDC 0x00030035
-#define CONFIG_MMDC_MDOTC 0x12554000
-#define CONFIG_MMDC_MDCFG0 0xbabf7954
-#define CONFIG_MMDC_MDCFG1 0xdb328f64
-#define CONFIG_MMDC_MDCFG2 0x01ff00db
-#define CONFIG_MMDC_MDMISC 0x00001680
-#define CONFIG_MMDC_MDREF 0x0f3c8000
-#define CONFIG_MMDC_MDRWD 0x00002000
-#define CONFIG_MMDC_MDOR 0x00bf1023
-#define CONFIG_MMDC_MDASP 0x0000003f
-#define CONFIG_MMDC_MPODTCTRL 0x0000022a
-#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
-
-
/*
* QIXIS Definitions
*/
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI