#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */
/* ticks per second */
-#define CFG_HZ (508469)
+#define CONFIG_SYS_HZ (508469)
/*-----------------------------------------------------------------------
* Stack sizes
#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
+#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/*----------------------------------------------------------------------
* Using SMC91C111 LAN chip
* Default IO base of chip is 0x300, Card Engine has this address lines
* (LAN chip) tied to Vcc, so we just care about the chip select
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC_USE_IOFUNCS
#endif /* __LPD7A404_10_H */