Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot...
[platform/kernel/u-boot.git] / include / configs / kmtegr1.h
index 69397ae..bdd35cc 100644 (file)
  * High Level Configuration Options
  */
 
-/* This needs to be set prior to including km/km83xx-common.h */
-
 #define CONFIG_HOSTNAME   "kmtegr1"
-#define CONFIG_KM_BOARD_NAME   "kmtegr1"
 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT      "ubi0"
 #define CONFIG_KM_UBI_PARTITION_NAME_APP       "ubi1"
 
-#define CONFIG_ENV_ADDR                0xF0100000
-#define CONFIG_ENV_OFFSET      0x100000
-
 #define CONFIG_NAND_ECC_BCH
 #define CONFIG_NAND_KMETER1
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define NAND_MAX_CHIPS                         1
 
-/* include common defines/options for all 8309 Keymile boards */
-#include "km/km8309-common.h"
+#define CONFIG_SYS_SICRL (0     \
+               | SICR_1_UART1_UART1RTS   \
+               | SICR_1_I2C_CKSTOP   \
+               | SICR_1_IRQ_A_IRQ    \
+               | SICR_1_IRQ_B_IRQ    \
+               | SICR_1_GPIO_A_GPIO    \
+               | SICR_1_GPIO_B_GPIO    \
+               | SICR_1_GPIO_C_GPIO    \
+               | SICR_1_GPIO_D_GPIO    \
+               | SICR_1_GPIO_E_LCS    \
+               | SICR_1_GPIO_F_GPIO    \
+               | SICR_1_USB_A_UART2S   \
+               | SICR_1_USB_B_UART2RTS   \
+               | SICR_1_FEC1_FEC1    \
+               | SICR_1_FEC2_FEC2    \
+       )
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 
-#define CONFIG_SYS_APP1_BASE           0xA0000000
-#define CONFIG_SYS_APP1_SIZE           256 /* Megabytes */
-#define CONFIG_SYS_APP2_BASE           0xB0000000
-#define CONFIG_SYS_APP2_SIZE           256 /* Megabytes */
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/*
- * Init Local Bus Memory Controller:
- *
- * Bank Bus     Machine PortSz  Size  Device
- * ---- ---     ------- ------  -----  ------
- *  2   Local   UPMA    16 bit  256MB APP1
- *  3   Local   GPCM    16 bit  256MB APP2
- *
- */
-
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
-                                BR_PS_16 | \
-                                BR_MS_GPCM | \
-                                BR_V)
-
-#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
-                                OR_GPCM_SCY_5 | \
-                                OR_GPCM_TRLX_CLEAR | \
-                                OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_APP2_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
-
-/*
- * MMU Setup
- */
-#define CONFIG_SYS_IBAT5L (0)
-#define CONFIG_SYS_IBAT5U (0)
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
-                                BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
-                                BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT6L      (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
-                                BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
-
-/* ethernet port connected to piggy (UEC2) */
-#define CONFIG_HAS_ETH1
-#define CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM                2       /* UCC3 */
-#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK12
-#define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR       0
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED        100
-
 #endif /* __CONFIG_H */