/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
-#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
+#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
+#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \
CONFIG_KM_PHRAM + \
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54
/* POST memory regions test */
-#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
/*
* IFC Definitions
*/
/* NOR Flash Definitions */
-#define CONFIG_SYS_FLASH_BASE 0x60000000
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE 0x60000000
+#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
-#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+#define CFG_SYS_NOR0_CSPR_EXT (0x0)
+#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_TE | \
CSPR_MSEL_NOR | \
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
+#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS }
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CFG_SYS_WRITE_SWAPPED_DATA
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
/* NAND Flash Definitions */
#define CFG_SYS_NAND_BASE 0x68000000
FTIM2_NAND_TWHRE(0x3c))
#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
-#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */
-#define CONFIG_SYS_QRIO_BASE 0x70000000
-#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE
+#define CFG_SYS_QRIO_BASE 0x70000000
+#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE
-#define CONFIG_SYS_CSPR2_EXT (0x00)
-#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+#define CFG_SYS_CSPR2_EXT (0x00)
+#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \
CSPR_PORT_SIZE_8 | \
CSPR_TE | \
CSPR_MSEL_GPCM | \
CSPR_V)
-#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
+#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024)
+#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \
CSOR_GPCM_TRHZ_20 | \
CSOR_GPCM_BCTLD)
-#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
FTIM0_GPCM_TEADC(0x8) | \
FTIM0_GPCM_TEAHC(0x2))
-#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
FTIM1_GPCM_TRAD(0x6))
-#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
FTIM2_GPCM_TCH(0x1) | \
FTIM2_GPCM_TWP(0x7))
-#define CONFIG_SYS_CS2_FTIM3 0x04000000
+#define CFG_SYS_CS2_FTIM3 0x04000000
/*
* Serial Port
*/
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
+#define CFG_SYS_NS16550_CLK get_serial_clock()
/*
* I2C
*/
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_MAX_HOPS 1
-#define CONFIG_SYS_NUM_I2C_BUSES 3
+#define CFG_SYS_I2C_MAX_HOPS 1
+#define CFG_SYS_NUM_I2C_BUSES 3
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x0
-#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
+#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{1, {I2C_NULL_HOP} }, \
}
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
-#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
-#define CONFIG_FSL_DEVICE_DISABLE
/*
* Miscellaneous configurable options
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize}\0" \
- "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
- "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ "erase " __stringify(CFG_SYS_FLASH_BASE) \
" +${filesize} && " \
"cp.b ${load_addr_r} " \
- __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \
"protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \
"set_fdthigh=true\0" \
"ethrotate=no\0" \
""
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
+#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */
#endif
projects / platform / kernel / u-boot.git / blobdiff